This invention relates generally to computer architectures and more particularly with a memory interface.
FIG. 1 illustrates a schematic block diagram of a computer system. As shown, the computer system includes a central processing unit (CPU) operably coupled to local cache and to a north bridge. The central processing unit when executing a memory transaction (e.g., a read from memory command, a write to memory command, or a read/write command) internally processes addresses associated with the transaction in virtual, or linear, address space. To communicate with the north bridge, the central processing unit converts the virtual addresses into physical addresses. The north bridge, upon receiving the physical addresses, determines whether the transaction is addressing a location within the accelerated graphics port (AGP) address space, the DRAM address space, or the PCI address space.
If the received physical address corresponds to the AGP address space, the north bridge further translates the physical address, using a GART table, into a corresponding physical address. Having obtained the physical address, the north bridge communicates with the memory to retrieve the appropriate memory block (e.g., line of memory, or multiple lines of memory where a line is 32 bits, 64 bits, 128 bits, etc.). If the physical address corresponds to the memory, the north bridge utilizes the physical address to facilitate the memory transaction. As such, if the memory transaction was a read transaction, the north bridge facilitates the retrieval of the corresponding memory line or lines from memory and provides them to the central processing unit. If the received physical address corresponds with the PCI address space, the north bridge passes the transaction to the PCI bus.
The south bridge, upon receiving a physical address, determines which of the plurality of I/O devices is to receive the transaction. To facilitate the forwarding of transactions to the I/O devices, the south bridge includes a plurality of memories, one for each I/O device coupled thereto, for queuing transactions to and from the corresponding I/O device. If an I/O device has a transaction queued, the south bridge, in a Round Robin manner, divides the PCI bus for transporting the queued transaction to the corresponding I/O device. As such, each I/O device has separate memory and therefore does not provide a dynamic interface.
In addition to the north bridge receiving transactions from the central processing unit, it may also receive transactions from the video graphics processor and the south bridge relaying transactions from I/O devices. Such transactions have varying requirements. For example, transactions from the central processing unit and video graphics processor are typically high speed transactions which require low latency. The amount of data in such transactions may vary but is generally a memory line or plurality of memory lines per transaction. The transactions from the I/O devices are generally large amounts of data (i.e., significantly more than several memory lines of data), but are typically latency tolerant.
In the system of FIG. 1, memory transactions are required to be synchronous with the processing speed of the memory. As such, the speed of transactions is restricted to the speed of memory. As is known in the art, improvements within the processing rate of the processing unit and the access rate of memory are increasing at different rates. Currently, the processors have a higher processing rate than the memory access rate of current memory devices. As such, the processing unit is not functioning at an optimal rate when performing memory transactions.
The video graphics processor provides display data to a display (not shown). Typically, the video graphics processor will include a frame buffer for storing at least part of a screen""s worth of data. To minimize the size of the frame buffer or to extend the memory used for generating the display data, the video graphics processor often uses the AGP memory space. In this instance, the video graphics processor is writing to and reading from the memory via the AGP bus and the north bridge. The processing of video graphics data requires a high speed low-latency transmission path. Since the video graphics processor is a separate integrated circuit from the north bridge, it experiences the same limitations as the central processing unit to north bridge interface.
In the system of FIG. 1, the central processing unit, the north bridge, the video graphics processor, the south bridge, are fabricated as separate integrated circuits. As such, the transmission path from the central processing unit through the north bridge to the memory is of a relatively significant length, in comparison to buses within the integrated circuits. As is known in the art, the length of a physical path impacts the speed at which data may be transmitted. Such restrictions arise due to the inductance and capacitance of such transmission paths. In short, the relatively substantial lengths of these paths limit the bandwidth capabilities and speed capabilities of processing transactions.
Within such a system, the memory includes dynamic random access memory (DRAM), which is accessed via a single memory bus. If the system requires additional parallel memory, the system employs additional DRAMs and an addition memory bus. But with each additional DRAM bus, the north bridge requires an additional memory controller. For example, if the system includes four DRAM buses, the north bridge includes four memory controllers. In addition, each device coupled to the north bridge needs to know which DRAM it is accessing such that it provides the appropriate address in the read and/or write transaction. Further, if the memory were changed, each device would need to be updated with the new memory configuration.
Therefore, a need exists for a method and apparatus for an improved memory interface that, among other things, allows memory to change without having to update the devices of a computing system and without such devices having to know which DRAM it is accessing.